MACHINE LEARNING PERFORMANCE MODELING AND DESIGN-SPACE EXPLORATION OF CMOS AMPLIFIERS AND GILBERT-CELL MIXER

Ali H Hamad

doi:10.33480/pilar.v22i2.8884

Authors

Ali H Hamad University of Baghdad

DOI:

https://doi.org/10.33480/pilar.v22i2.8884

Keywords:

analog design automation, gilbert-cell mixer, machine learning, surrogate modeling, transistor sizing

Abstract

Analog and radio-frequency integrated-circuit sizing commonly relies on repeated manual analysis and SPICE simulation. This study investigates supervised regression models as computationally efficient surrogates for estimating circuit performance from device geometry, bias settings, and passive-component values. Three CMOS circuits were examined: a common-source amplifier, a cascode amplifier, and a double-balanced Gilbert-cell down-conversion mixer. Extensive SPICE sweeps generated 40,068 labelled design samples covering ten performance metrics, including bandwidth, power consumption, voltage gain, conversion gain, intermediate-frequency output swing, and noise figure. Linear regression, random forest, gradient-boosted trees, and multilayer perceptron models were compared using identical 80/20 data partitions. After input and target standardization, the multilayer perceptron achieved R² values of at least 0.9987 with normalized RMSE below 0.8% for all targets. Surrogate inference required only microseconds per design point, substantially reducing evaluation time compared with transistor-level simulation. Feature-importance analysis revealed relevant design sensitivities, while Pareto analysis of 200,000 surrogate evaluations per circuit identified gain-bandwidth-power and gain-noise-power trade-offs. Additional tests examined split sensitivity, leave-one-region-out generalization, uncertainty estimation, and agreement between surrogate-selected Pareto candidates and transistor-level results. The study is limited to schematic-level, single-corner data without process-voltage-temperature variation, mismatch, layout parasitics, IIP3, or cross-topology transfer. The resulting datasets and benchmarks provide a reproducible basis for machine-learning-assisted analog design automation.

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References

Afacan, E., Lourenço, N., Martins, R., & Dündar, G. (2021). Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test. Integration, the VLSI Journal, 77, 113–130. https://doi.org/10.1016/j.vlsi.2020.11.006

Barros, M. F. M., Guilherme, J. M. C., & Horta, N. C. G. (2010). Analog circuits optimization based on evolutionary computation techniques. Integration, the VLSI Journal, 43(1), 136–155. https://doi.org/10.1016/j.vlsi.2009.09.001

Breiman, L. (2001). Random forests. Machine Learning, 45(1), 5–32. https://doi.org/10.1023/a:1010933404324

Budak, A. F., Bhansali, P., Liu, B., Sun, N., Pan, D. Z., & Kashyap, C. V. (2021). DNN-Opt: An RL inspired optimization for analog circuit sizing using deep neural networks. 2021 58th ACM/IEEE Design Automation Conference (DAC), 1219–1224. https://doi.org/10.1109/dac18074.2021.9586139

Cao, W., Gao, J., Ma, T., Ma, R., Benosman, M., & Zhang, X. (2025). RoSE-Opt: Robust and efficient analog circuit parameter optimization with knowledge-infused reinforcement learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(2), 627–640. https://doi.org/10.1109/tcad.2024.3435692

Devi, S., Tilwankar, G., & Zele, R. (2021). Automated design of analog circuits using machine learning techniques. 2021 25th International Symposium on VLSI Design and Test (VDAT), 1–6. https://doi.org/10.1109/vdat53777.2021.9601131

Fayazi, M., Colter, Z., Afshari, E., & Dreslinski, R. (2021). Applications of artificial intelligence on the modeling and optimization for analog and mixed-signal circuits: A review. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(6), 2418–2431. https://doi.org/10.1109/tcsi.2021.3065332

Friedman, J. H. (2001). Greedy function approximation: A gradient boosting machine. The Annals of Statistics, 29(5), 1189–1232. https://doi.org/10.1214/aos/1013203451

Gielen, G. G. E., & Rutenbar, R. A. (2000). Computer-aided design of analog and mixed-signal integrated circuits. Proceedings of the IEEE, 88(12), 1825–1854. https://doi.org/10.1109/5.899053

Gilbert, B. (1968). A precise four-quadrant multiplier with subnanosecond response. IEEE Journal of Solid-State Circuits, 3(4), 365–373. https://doi.org/10.1109/jssc.1968.1049925

Gray, P. R., Hurst, P. J., Lewis, S. H., & Meyer, R. G. (2009). Analysis and design of analog integrated circuits (5th ed.). Hoboken, NJ: Wiley.

Hakhamaneshi, K., Nassar, M., Phielipp, M., Abbeel, P., & Stojanović, V. (2023). Pretraining graph neural networks for few-shot analog circuit modeling and design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(7), 2163–2173. https://doi.org/10.1109/tcad.2022.3217421

Hakhamaneshi, K., Werblun, N., Abbeel, P., & Stojanović, V. (2019). BagNet: Berkeley analog generator with layout optimizer boosted with deep neural networks. 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1–8. https://doi.org/10.1109/iccad45719.2019.8942062

Hornik, K., Stinchcombe, M., & White, H. (1989). Multilayer feedforward networks are universal approximators. Neural Networks, 2(5), 359–366. https://doi.org/10.1016/0893-6080(89)90020-8

Kingma, D. P., & Ba, J. (2015). Adam: A method for stochastic optimization. In Proceedings of the 3rd International Conference on Learning Representations (pp. 1–15). San Diego, CA.

Lai, Y., Lee, S., Chen, G., Poddar, S., Hu, M., Pan, D. Z., & Luo, P. (2025). AnalogCoder: Analog circuit design via training-free code generation. Proceedings of the AAAI Conference on Artificial Intelligence, 39(1), 379–387. https://doi.org/10.1609/aaai.v39i1.32016

Lee, T. H. (2004). The design of CMOS radio-frequency integrated circuits (2nd ed.). Cambridge, UK: Cambridge University Press.

Li, Y., Wang, Y., Li, Y., Zhou, R., & Lin, Z. (2020). An artificial neural network assisted optimization system for analog design space exploration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10), 2640–2653. https://doi.org/10.1109/tcad.2019.2961322

Liu, B., Gielen, G., & Fernández, F. V. (2014). Automated design of analog and high-frequency circuits: A computational intelligence approach. Berlin, Germany: Springer.

Lourenço, N., Afacan, E., Martins, R., Passos, F., Canelas, A., Póvoa, R., … Dündar, G. (2018). On the exploration of promising analog IC designs via artificial neural networks. 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 133–136. https://doi.org/10.1109/smacd.2018.8434896

Lyu, W., Yang, F., Yan, C., Zhou, D., & Zeng, X. (2018). Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design. In Proceedings of the 35th International Conference on Machine Learning (pp. 3306–3314). Stockholm, Sweden: PMLR. https://doi.org/

Mina, R., Jabbour, C., & Sakr, G. E. (2022). A review of machine learning techniques in analog integrated circuit design automation. Electronics, 11(3), 435. https://doi.org/10.3390/electronics11030435

Pedregosa, F., Varoquaux, G., Gramfort, A., Michel, V., Thirion, B., Grisel, O., … Duchesnay, É. (2011). Scikit-learn: Machine learning in Python. Journal of Machine Learning Research, 12, 2825–2830. https://doi.org/

Razavi, B. (2012). RF microelectronics (2nd ed.). Upper Saddle River, NJ: Prentice Hall.

Razavi, B. (2017). Design of analog CMOS integrated circuits (2nd ed.). New York, NY: McGraw-Hill.

Rutenbar, R. A., Gielen, G. G. E., & Roychowdhury, J. (2007). Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs. Proceedings of the IEEE, 95(3), 640–669. https://doi.org/10.1109/jproc.2006.889371

Settaluri, K., Haj-Ali, A., Huang, Q., Hakhamaneshi, K., & Nikolić, B. (2020). AutoCkt: Deep reinforcement learning of analog circuit designs. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 490–495. https://doi.org/10.23919/date48585.2020.9116200

Wang, H., Wang, K., Yang, J., Shen, L., Sun, N., Lee, H.-S., & Han, S. (2020). GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning. 2020 57th ACM/IEEE Design Automation Conference (DAC), 1–6. https://doi.org/10.1109/dac18072.2020.9218757

Wolfe, G., & Vemuri, R. (2003). Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(2), 198–212. https://doi.org/10.1109/tcad.2002.806600

Zhang, Q.-J., Gupta, K. C., & Devabhaktuni, V. K. (2003). Artificial neural networks for RF and microwave design: From theory to practice. IEEE Transactions on Microwave Theory and Techniques, 51(4), 1339–1350. https://doi.org/10.1109/tmtt.2003.809179